SrasV1, France, Analysis, bibRecord, 000061

Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Identifieur interne : 000061 ( France/Analysis ); précédent : 000060; suivant : 000062

Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Auteurs : R. Silveira Feitoza [France] ; Manuel J. Barragan [France] ; D. Dzahini [France] ; S. Mir [France]

Source :

IEEE Transactions on Device and Materials Reliability [ 1530-4388 ] ; 2019.

RBID : Hal:hal-01989117

Abstract

Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution Incremental Sigma-Delta converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.

Url:

https://hal.archives-ouvertes.fr/hal-01989117

DOI: 10.1109/TDMR.2019.2891298

Affiliations:

Links toward previous steps (curation, corpus...)

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Hal:hal-01989117

Le document en format XML

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              <country key="FR"></country>
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            <ref type="url">http://tima.univ-grenoble-alpes.fr/</ref>
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          <orgName>Institut polytechnique de Grenoble - Grenoble Institute of Technology</orgName>
          <orgName type="acronym">Grenoble INP</orgName>
          <date type="start">2007-01-01</date>
          <desc>            <address>              <addrLine>46 avenue Félix Viallet 38031 Grenoble Cedex 1</addrLine>
              <country key="FR"></country>
            </address>
            <ref type="url">http://www.grenoble-inp.fr/</ref>
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<tutelle name="UMR5159" active="#struct-441569" type="direct"><org type="institution" xml:id="struct-441569" status="VALID">          <idno type="IdRef">02636817X</idno>
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          <orgName>Centre National de la Recherche Scientifique</orgName>
          <orgName type="acronym">CNRS</orgName>
          <date type="start">1939-10-19</date>
          <desc>            <address>              <country key="FR"></country>
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<tutelle active="#struct-445543" type="direct"><org type="institution" xml:id="struct-445543" status="VALID">          <idno type="IdRef">188399275</idno>
          <orgName>Université Grenoble Alpes</orgName>
          <orgName type="acronym">UGA</orgName>
          <date type="start">2016-01-01</date>
          <desc>            <address>              <addrLine>CS 40700 - 38058 Grenoble cedex</addrLine>
              <country key="FR"></country>
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            <ref type="url">http://www.univ-grenoble-alpes.fr</ref>
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</hal:affiliation>
<country>France</country>
<placeName><settlement type="city">Grenoble</settlement>
<region type="region" nuts="2">Auvergne-Rhône-Alpes</region>
<region type="old region" nuts="2">Rhône-Alpes</region>
</placeName>
<orgName type="university">Université Grenoble-Alpes</orgName>
</affiliation>
</author>
<author><name sortKey="Mir, S" sort="Mir, S" uniqKey="Mir S" first="S." last="Mir">S. Mir</name>
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          <orgName>Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés</orgName>
          <orgName type="acronym">TIMA</orgName>
          <date type="start">2007-01-01</date>
          <desc>            <address>              <addrLine>46 avenue Félix Viallet38031 GRENOBLE Cedex 1</addrLine>
              <country key="FR"></country>
            </address>
            <ref type="url">http://tima.univ-grenoble-alpes.fr/</ref>
          </desc>
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          <orgName>Institut polytechnique de Grenoble - Grenoble Institute of Technology</orgName>
          <orgName type="acronym">Grenoble INP</orgName>
          <date type="start">2007-01-01</date>
          <desc>            <address>              <addrLine>46 avenue Félix Viallet 38031 Grenoble Cedex 1</addrLine>
              <country key="FR"></country>
            </address>
            <ref type="url">http://www.grenoble-inp.fr/</ref>
          </desc>
        </org>
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          <orgName>Centre National de la Recherche Scientifique</orgName>
          <orgName type="acronym">CNRS</orgName>
          <date type="start">1939-10-19</date>
          <desc>            <address>              <country key="FR"></country>
            </address>
            <ref type="url">http://www.cnrs.fr/</ref>
          </desc>
        </org>
</tutelle>
<tutelle active="#struct-445543" type="direct"><org type="institution" xml:id="struct-445543" status="VALID">          <idno type="IdRef">188399275</idno>
          <orgName>Université Grenoble Alpes</orgName>
          <orgName type="acronym">UGA</orgName>
          <date type="start">2016-01-01</date>
          <desc>            <address>              <addrLine>CS 40700 - 38058 Grenoble cedex</addrLine>
              <country key="FR"></country>
            </address>
            <ref type="url">http://www.univ-grenoble-alpes.fr</ref>
          </desc>
        </org>
</tutelle>
</tutelles>
</hal:affiliation>
<country>France</country>
<placeName><settlement type="city">Grenoble</settlement>
<region type="region" nuts="2">Auvergne-Rhône-Alpes</region>
<region type="old region" nuts="2">Rhône-Alpes</region>
</placeName>
<orgName type="university">Université Grenoble-Alpes</orgName>
</affiliation>
</author>
</analytic>
<idno type="DOI">10.1109/TDMR.2019.2891298</idno>
<series><title level="j">IEEE Transactions on Device and Materials Reliability</title>
<idno type="ISSN">1530-4388</idno>
<imprint><date type="datePub">2019</date>
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<front><div type="abstract" xml:lang="en">              <p>Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution Incremental Sigma-Delta converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.</p>
            </div>
</front>
</TEI>
<affiliations><list><country><li>France</li>
</country>
<region><li>Auvergne-Rhône-Alpes</li>
<li>Rhône-Alpes</li>
</region>
<settlement><li>Grenoble</li>
</settlement>
<orgName><li>Université Grenoble-Alpes</li>
</orgName>
</list>
<tree><country name="France"><region name="Auvergne-Rhône-Alpes"><name sortKey="Silveira Feitoza, R" sort="Silveira Feitoza, R" uniqKey="Silveira Feitoza R" first="R." last="Silveira Feitoza">R. Silveira Feitoza</name>
</region>
<name sortKey="Barragan, Manuel J" sort="Barragan, Manuel J" uniqKey="Barragan M" first="Manuel J." last="Barragan">Manuel J. Barragan</name>
<name sortKey="Dzahini, D" sort="Dzahini, D" uniqKey="Dzahini D" first="D." last="Dzahini">D. Dzahini</name>
<name sortKey="Mir, S" sort="Mir, S" uniqKey="Mir S" first="S." last="Mir">S. Mir</name>
</country>
</tree>
</affiliations>
</record>

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Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

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